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SPRI: Simulator Partitioning Research Infrastructure
[abstract] (PDF)
Zhuo Ruan, Koy Rehme, and David A. Penry
Proceedings of the 3rd Workshop on Architectural Research Prototyping
(WARP), June 2008.
Using FPGAs as architectural simulation accelerators has been widely
discussed in the computer architecture design community. We previously
proposed a hybrid SW/HW simulation infrastructure named SPRI
(Simulator Partitioning Research Infrastructure) which automatically
partitions the general timing model into the software and hardware
portions for simulation speedup, conforming to the set-based
partitioning specification. The SPRI platform takes two main
inputs—partitioning specification and the architectural model; it then
produces a modified SW architectural binary and a HW-accelerated RTL
description which can communicate with each other, called hybrid SW/HW
co-simulator—the final output of SPRI. Various experiment cases have
been also run through the SPRI infrastructure to test its partitioning
functionality and API wrapper generation.