Welcome
1:30-1:40 pm
David Penry, Brigham Young University

Session 1: Tools and Techniques
Session Chair: Krste Asanović, UC Berkeley

1:40 pm - 2:00 pm
Hybrid CPU/FPGA Performance Models
Angshuman Parashar, Michael Adler, Michael Pellauer, Joel Emer
Intel, MIT

2:00 pm - 2:20 pm
SPRI: Simulator Partitioning Research Infrastructure
Zhuo Ruan, Koy Rehme, David Penry
Brigham Young University

2:20 pm - 2:40 pm
Unified Modeling Abstraction for Fast Simulation and Acceleration
Gummidipudi Krishnaiah, Preeti Ranjan Panda, Ashok Jagannathan, Sreenivas Subramoney, Anshul Kumar
Indian Institute of Technology Delhi, Intel Technology India

2:40 pm - 3:00 pm
Modeling FPGA-Based Cyber-Physical Systems
Dan Fay, Graham Schelle, Li Shang, Dirk Grunwald
University of Colorado at Boulder

Break
3:00 pm - 3:30 pm

Session 2: Hybrid Performance Modeling
Session Chair: David Penry, BYU

3:30 pm - 3:50 pm
An MP Architectural Exploration Vehicle using FPGA-accelerated Simulation
Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
Carnegie Mellon University

3:50 pm - 4:10 pm
An FPGA Host-Multithreaded Functional Model for SPARC v8
Zhangxi Tan, Krste Asanović, David Patterson
UC Berkeley

4:10 pm - 4:30 pm
Lessons from Implementing a FAST Prototype
Derek Chiou, Dam Sunwoo, Nikhil Patil, Joonsoo Kim, Bill Reinhart, Hari Angepat, D. Eric Johnson
University of Texas at Austin

Panel Discussion: Prototyping vs. Performance modeling on FPGAs
4:30 pm - 5:30 pm
Moderated by Arvind, MIT

Panel members
Krste Asanović, UC Berkeley
Derek Chiou, UT Austin
Joel Emer, Intel
Shih-Lien Lu, Intel

Session 3: Experiences in Prototyping
Session Chair: Shih-Lien Lu, Intel

9:00 am - 9:20 am
Implementation of Power Efficient High Performance FPU for SCOORE
W. Ashmawi, J. Burr, A. Sharma, J. Renau
UC Santa Cruz

9:20 am - 9:40 am
The XMT FPGA Prototype/Cycle-Accurate-Emulator Hybrid
Xingzhi Wen, Uzi Vishkin
University of Maryland

9:40 am - 10:00 am
Exploring Varying Levels of Hardware Reliability in Processor Architectures
Graham Schelle, Dan Fay, Li Shang, Dirk Grunwald
University of Colorado at Boulder

10:00 am - 10:20 am
L3NIC: An in-system FPGA prototype for coherent NIC device on FSB
Zhihong Yu, Ling Liu, Bhushan Chitiur, Paul M. Stillwell Jr, Yong Zhang, Shunyu Zhu, Chuanhua Song, Lu Cao, Dong Liu
Intel

Break
10:20 am - 10:50 am

Session 4: Prototyping and Emulation Platforms
Session Chair: Dong Liu, Intel

10:50 am - 11:10 am
Single FPGA Chip Small Scale Multiprocessor as Building Blocks for Large Scale Multiprocessors on Large Scale Multi-FPGA Emulator
Xinyu Li, Omar Hammami
ENSTA

11:10 am - 11:30 am
FPGA Based Tera-Scale IA Prototyping System
Thorsten Mattner, Franz W. Olbrich
Intel

Discussion session
11:30 am - 12:00 pm

Open microphone for discussion